Power consumption is one of the top concerns of Very Large Scale Integration (VLSI) circuit designs, for which CMOS is the primary technology. Low-power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. The power dissipation can be categorized in two parts: Dynamic and Static power. Dynamic power consumption was previously the single largest concern for low-power chip designers since dynamic power accounted for 90% or more of the total chip power. However, as the feature size shrinks, static power has become a great challenge for current and future technologies. With increasing chip densities, leakage power has become dominant in memory design. This project's focus is to reduce leakage power consumption of a 16*4 byte SRAM in 0.18Îźm GPDK process by employing techniques of power gating and dual threshold voltage design. By implementing the sleep transistor technique we are aiming to save power with a marginal increase in the access delay and associated area over head.